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IP4338CX24/LF
10-channel integrated filter network with ESD input protection to IEC 61000-4-2 level 4
Rev. 02 -- 20 August 2009 Product data sheet
1. Product profile
1.1 General description
The IP4338CX24/LF is a 10-channel RC low-pass filter array which is designed to provide filtering of undesired RF signals in the 800 MHz to 3000 MHz frequency band. In addition, the IP4338CX24/LF incorporates diodes to provide protection to downstream components from ElectroStatic Discharge (ESD) voltages as high as 15 kV. The IP4338CX24/LF is fabricated using monolithic silicon technology and integrates 10 resistors and 20 diodes in a single Wafer-Level Chip-Scale Package (WLCSP) measuring 1.96 mm by 2.01 mm (typical). These features make the IP4338CX24/LF ideal for use in applications requiring the utmost in miniaturization.
1.2 Features
I I I I Pb-free, RoHS compliant and free of halogen and antimony (Dark Green compliant) Integrated 10-channel -type RC filter network 70 series resistance; 25 pF (typical) capacitance per line Integrated ESD protection withstanding 15 kV contact discharge, far exceeding IEC 61000-4-2 level 4 I WLCSP with 0.4 mm pitch
1.3 Applications
I Cellular and Personal Communication System (PCS) mobile handsets I Cordless telephones I Wireless data (WAN/LAN) systems
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
2. Pinning information
2.1 Pinning
bump A1 index area 1
IP4338CX24/LF
2 3 4 5
A
B
C
D
E
008aaa183
Transparent top view
Fig 1.
Pin configuration IP4338CX24/LF
2.2 Pin description
Table 1. Pin A2 and A5 A1 and A4 B2 and B5 B1 and B4 C2 and C5 C1 and C4 D2 and D5 D1 and D4 E2 and E5 E1 and E4 A3, C3, D3, E3 B3 Pinning Description filter channel 1 filter channel 2 filter channel 3 filter channel 4 filter channel 5 filter channel 6 filter channel 7 filter channel 8 filter channel 9 filter channel 10 ground no ball
3. Ordering information
Table 2. Ordering information Package Name IP4338CX24/LF
IP4338CX24LF_2
Type number
Description wafer level chip-size package; 24 bumps; 1.96 x 2.01 x 0.61 mm
Version IP4338CX24/LF
(c) NXP B.V. 2009. All rights reserved.
WLCSP24
Product data sheet
Rev. 02 -- 20 August 2009
2 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
4. Functional diagram
Rs(ch)
A1, A2, B1, B2, C1, C2, D1, D2, E1, E2
A4, A5, B4, B5, C4, C5, D4, D5, E4, E5
A3, C3, D3, E3
008aaa182
Fig 2.
Schematic diagram IP4338CX24/LF
5. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VI VESD Parameter input voltage electrostatic discharge voltage all pins to ground contact discharge air discharge IEC 61000-4-2 level 4; all pins to ground contact discharge air discharge Ich Pch Ptot Tstg Tamb
[1]
[1] [1]
Conditions
Min -0.5 -15 -15
Max +5.5 +15 +15
Unit V kV kV
-8 -15 -55
+8 +15 33 60 250 +150 260 +85
kV kV mA mW mW C C C
channel current (DC) channel power dissipation total power dissipation storage temperature
Tamb = 70 C continuous power; Tamb = 70 C continuous power; Tamb = 70 C 10 s maximum
Treflow(peak) peak reflow temperature ambient temperature
-30
Device is qualified with 1000 pulses of 15 kV contact discharges each, according to the IEC61000-4-2 model and far exceeds the specified level 4 (8 kV contact discharge).
IP4338CX24LF_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 20 August 2009
3 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
6. Characteristics
Table 4. Channel characteristics Tamb = 25 C; unless otherwise specified. Symbol Parameter Rs(ch) Cch VBR ILR
[1]
Conditions Vbias(DC) = 0 V; f = 1 MHz Itest = 1 mA per channel; VI = 3.0 V
[1]
Min 52.5 6 -
Typ 70 25 -
Max 87.5 30 20 20
Unit pF V nA
channel series resistance f = 0 Hz (DC) channel capacitance breakdown voltage reverse leakage current
Guaranteed by design.
Table 5. Frequency characteristics Tamb = 25 C; unless otherwise specified. Symbol Parameter il ct insertion loss crosstalk attenuation Conditions 800 MHz < f < 3 GHz; Rgen = 50 ; RL = 50 800 MHz < f < 3 GHz; Rgen = 50 ; RL = 50 Min Typ 20 25 Max Unit dB dB
IP4338CX24LF_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 20 August 2009
4 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
7. Application information
7.1 Insertion loss
The insertion loss measurement configuration of a typical 50 NetWork Analyzer (NWA) system for evaluation of the IP4338CX24/LF is shown in Figure 3. As an example, the insertion loss of channels between pins A2 and A5, A1 and A4, C1 and C4, E2 and E5, E1 and E4 at frequencies up to 6 GHz is displayed in Figure 4. The insertion loss is measured with a test PCB utilizing laser drilled micro-via holes that connect the PCB ground plane to the IP4338CX24/LF ground pins.
IN
50
DUT
OUT
50
TEST BOARD
Vgen
001aai755
Fig 3.
Frequency response measurement configuration
0 s21 (dB) -10 -20 -30 -40 -50
(4) (1) (2) (3)
001aaj952
-60
(5)
-70 10-1
1
10
102
103 f (MHz)
104
(1) Channel 10 (pins E1 and E4). (2) Channel 9 (pins E2 and E5). (3) Channel 1 (pins A2 and A5). (4) Channel 2 (pins A1 and A4). (5) Channel 6 (pins C1 and C4).
Fig 4.
Measured insertion loss magnitudes
IP4338CX24LF_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 20 August 2009
5 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
7.2 Crosstalk
The crosstalk measurement configuration of a typical 50 NWA system for evaluation of the IP4338CX24/LF is shown in Figure 5. The measured crosstalk within the IP4338CX24/LF in a 50 NWA system from one channel to another is shown in Figure 6 for five different pairs of channels. In all cases, unused connections are terminated with 50 to ground.
IN_1
50
DUT
OUT_2 OUT_1
50 50
IN_2
50
TEST BOARD
Vgen
001aai756
Fig 5.
Crosstalk measurement configuration
0 ct (dB) -10 -20
(5)
001aaj953
-30 -40 -50 -60 -70 10-1
(4) (3) (2) (1)
1
10
102
103 f (MHz)
104
(1) Channels 2 and 6 (pins A1 and C4). (2) Channels 2 and 10 (pins A1 and E4). (3) Channels 3 and 7 (pins B2 and D5). (4) Channels 5 and 3 (pins C2 and B5). (5) Channels 5 and 7 (pins C2 and D5).
Fig 6.
Measured crosstalk between adjacent channels
IP4338CX24LF_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 20 August 2009
6 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
8. Package outline
WLCSP24: wafer level chip-size package; 24 bumps; 1.96 x 2.01 x 0.61 mm IP4338CX24/LF
D
B
A
bump A1 index area A2 E A
A1
detail X
e1 e b
E e D e2
C
B
A 1 2 3 4 5 X
0 Dimensions Unit mm A A1 A2 b D E e 0.4 e1 1.6 e2 1.6
1 scale
2 mm
max 0.66 0.22 0.31 2.01 2.06 nom 0.61 0.20 0.41 0.26 1.96 2.01 min 0.56 0.18 0.21 1.91 1.96
ip4338cx24_lf_po
Outline version IP4338CX24/LF
References IEC JEDEC JEITA
European projection
Issue date 09-03-25 09-05-19
Fig 7.
Package outline IP4338CX24/LF (WLCSP24)
(c) NXP B.V. 2009. All rights reserved.
IP4338CX24LF_2
Product data sheet
Rev. 02 -- 20 August 2009
7 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
9. Soldering of WLCSP packages
9.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note AN10439 "Wafer Level Chip Scale Package" and in application note AN10365 "Surface mount reflow soldering description". Wave soldering is not suitable for this package. All NXP WLCSP packages are lead-free.
9.2 Board mounting
Board mounting of a WLCSP requires several steps: 1. Solder paste printing on the PCB 2. Component placement with a pick and place machine 3. The reflow soldering itself
9.3 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 8) than a PbSn process, thus reducing the process window
* Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 6.
Table 6. Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 8.
IP4338CX24LF_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 20 August 2009
8 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 8.
Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365 "Surface mount reflow soldering description".
9.3.1 Stand off
The stand off between the substrate and the chip is determined by:
* The amount of printed solder on the substrate * The size of the solder land on the substrate * The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal Expansion Coefficient) differences between substrate and chip.
9.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after reflow can be done with X-ray to monitor defects such as bridging, open circuits and voids.
9.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip will be damaged. In that case it is recommended not to re-use the chip again.
IP4338CX24LF_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 20 August 2009
9 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. Removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. The surface of the substrate should be carefully cleaned and all solder and flux residues and/or underfill removed. When a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To reflow the solder, use the solder profile shown in application note AN10365 "Surface mount reflow soldering description".
9.3.4 Cleaning
Cleaning can be done after reflow soldering.
10. Abbreviations
Table 7. Acronym DUT ESD LAN NWA PCB PCS RoHS WAN WLCSP Abbreviations Description Device Under Test ElectroStatic Discharge Local Area Network NetWork Analyzer Printed-Circuit Board Personal Communication System Restriction of Hazardous Substances Wide Area Network Wafer-Level Chip-Scale Package
11. Revision history
Table 8. Revision history Release date 20090820 Data sheet status Product data sheet Product data sheet Change notice Supersedes IP4338CX24LF_1 Document ID IP4338CX24LF_2 Modifications: IP4338CX24LF_1
*
Figure 4: figure title and symbol changed
20090618
IP4338CX24LF_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 20 August 2009
10 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
12. Legal information
12.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
12.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
IP4338CX24LF_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 20 August 2009
11 of 12
NXP Semiconductors
IP4338CX24/LF
10-channel integrated filter network with ESD input protection
14. Contents
1 1.1 1.2 1.3 2 2.1 2.2 3 4 5 6 7 7.1 7.2 8 9 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 10 11 12 12.1 12.2 12.3 12.4 13 14 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Application information. . . . . . . . . . . . . . . . . . . 5 Insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Soldering of WLCSP packages. . . . . . . . . . . . . 8 Introduction to soldering WLCSP packages . . . 8 Board mounting . . . . . . . . . . . . . . . . . . . . . . . . 8 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . 8 Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Quality of solder joint . . . . . . . . . . . . . . . . . . . . 9 Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 August 2009 Document identifier: IP4338CX24LF_2

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